A cell array of a NAND flash device includes a plurality of cell blocks. Each cell block is operated with a cell array divided into strings, unlike a common flash device. Due to this characteristic, a drain contact connected to a bit line and a source contact for global ground are positioned at both ends of the string. These contacts are connected to the junction of a select transistor for string control.
A process of forming a source contact plug and a drain contact plug of a general flash device is described in short. A plurality of string structures are formed on a semiconductor substrate, including a source select transistor, a plurality of memory cells, and a drain select transistor. A first interlayer insulating film is formed on the string structures. A first contact hole through which the source of the source select transistor is exposed is then formed. A barrier metal layer (Ti/TiN) and a tungsten (W) layer are laminated over the first interlayer insulating film including the first contact hole. A Chemical Mechanical Polishing (CMP) process is then performed to form a source contact plug that gap fills the first contact hole. After a second interlayer insulating film is formed on the source contact plug, a second contact hole through which the drain of the drain select transistor is exposed is formed. A polysilicon film is then deposited on the second interlayer insulating film including the second contact hole. A CMP process is then performed to form a drain contact plug that gap fills the second contact hole.
However, in the process of forming the source contact plug using the CMP process, residues of the barrier metal layer or the tungsten (W) layer remain on the first interlayer insulating film. If the region on which the conductive residues remain is a region where the drain contact plug is formed, neighboring drain contact plugs are interconnected by the conductive residues, so a bridge is generated. A bridge between the drain contact plugs is also generated due to abnormal oxidization of tungsten (W) of the conductive residues. In this case, the bridge causes the bit line leakage current, resulting in a low yield.
Furthermore, at the time of a wet etch process for forming the drain contact hole, etch damage causes an open path to be generated at the interface of the first interlayer insulating film and the second interlayer insulating film. In this case, when depositing the polysilicon film on the contact hole, neighboring drain contact plugs are interconnected through the open path, thus generating a bridge and bit line failure.